Review Questions12.1 What general roles are performed by processor registers?12.2 What categories of data are commonly supported by user-visible registers?12.3 What is the function of condition codes?12.4 What is a program status word?12.5 Why is a two-stage instruction pipeline unlikely to cut the instruction cycle time inhalf, compared with the use of no pipeline?12.6 List and briefly explain various ways in which an instruction pipeline can deal withconditional branch instructions.12.7 How are history bits used for branch prediction?Problems12.1 a. If the last operation performed on a computer with an 8-bit word was an additionin which the two operands were 00000010 and 00000011, what would be the valueof the following flags?. Carry. Zero.

1. Other Words For Status

Overflow. Sign. Even Parity.

Half-Carryb. Repeat for the addition of (twos complement) and.12.2 Repeat Problem 12.1 for the operation A B, where A contains 11110000 and Bcontains 0010100.12.3 A microprocessor is clocked at a rate of 5 GHz.a. How long is a clock cycle?b. What is the duration of a particular type of machine instruction consisting of threeclock cycles?12.4 A microprocessor provides an instruction capable of moving a string of bytes fromone area of memory to another. The fetching and initial decoding of the instruction- 1 + 112.8 / KEY TERMS, REVIEW QUESTIONS,AND PROBLEMS 477takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer each byte.The microprocessoris clocked at a rate of 10 GHz.a. Determine the length of the instruction cycle for the case of a string of 64 bytes.b. What is the worst-case delay for acknowledging an interrupt if the instruction isnoninterruptible?c.

Repeat part (b) assuming the instruction can be interrupted at the beginning ofeach byte transfer.12.5 The Intel 8088 consists of a bus interface unit (BIU) and an execution unit (EU),which form a 2-stage pipeline. The BIU fetches instructions into a 4-byte instructionqueue.The BIU also participates in address calculations, fetches operands, and writesresults in memory as requested by the EU. If no such requests are outstanding and thebus is free, the BIU fills any vacancies in the instruction queue.When the EU completesexecution of an instruction, it passes any results to the BIU (destined for memoryor I/O) and proceeds to the next instruction.a. Suppose the tasks performed by the BIU and EU take about equal time. By whatfactor does pipelining improve the performance of the 8088?

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Ignore the effect ofbranch instructions.b. Repeat the calculation assuming that the EU takes twice as long as the BIU.12.6 Assume an 8088 is executing a program in which the probability of a program jump is0.1. For simplicity, assume that all instructions are 2 bytes long.a. What fraction of instruction fetch bus cycles is wasted?b.

Repeat if the instruction queue is 8 bytes long.12.7 Consider the timing diagram of Figures 12.10. Assume that there is only a two-stagepipeline (fetch, execute). Redraw the diagram to show how many time units are nowneeded for four instructions.12.8 Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculateaddresses (DA), fetch operand (FO), and execute (EX). Draw a diagram similarto Figures 12.10 for a sequence of 7 instructions, in which the third instruction is abranch that is taken and in which there are no data dependencies.12.9 A pipelined processor has a clock rate of 2.5 GHz and executes a program with1.5 million instructions. The pipeline has five stages, and instructions are issued ata rate of one per clock cycle.

Ignore penalties due to branch instructions and outof-sequence executions.a. What is the speedup of this processor for this program compared to a nonpipelinedprocessor, making the same assumptions used in Section 12.4?b. What is throughput (in MIPS) of the pipelined processor?12.10 A nonpipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles perinstruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However,due to internal pipeline delays, such as latch delay, the clock rate of the newprocessor has to be reduced to 2 GHz.a.

What is the speedup achieved for a typical program?b. What is the MIPS rate for each processor?12.11 Consider an instruction sequence of length n that is streaming through the instructionpipeline. Let p be the probability of encountering a conditional or unconditional branchinstruction, and let q be the probability that execution of a branch instruction I causes ajump to a nonconsecutive address.Assume that each such jump requires the pipeline tobe cleared, destroying all ongoing instruction processing, when I emerges from the laststage. Revise Equations (12.1) and (12.2) to take these probabilities into account.12.12 One limitation of the multiple-stream approach to dealing with branches in a pipelineis that additional branches will be encountered before the first branch is resolved.Suggest two additional limitations or drawbacks.12.13 Consider the state diagrams of Figure 12.28.

Compare these with the branch prediction state diagram in Section 12.4. The number of times the DBNE loop is executed and the contents of the three registerswhen the NOP instruction is reached.b. Repeat (a), but now assume that memory between $4000 and $4FEE is loadedwith $0000 and between $5000 and $6000 is loaded with $AAA.12.15 Redraw Figures 12.19c, assuming that the conditional branch is not taken.12.16 Table 12.5 summarizes statistics from MACD84 concerning branch behavior forvarious classes of applications.With the exception of type 1 branch behavior, there isno noticeable difference among the application classes.

Determine the fraction of allbranches that go to the branch target address for the scientific environment. Repeatfor commercial and systems environments.12.17 Pipelining can be applied within the ALU to speed up floating-point operations. Considerthe case of floating-point addition and subtraction. In simplified terms, thepipeline could have four stages: (1) Compare the exponents; (2) Choose the exponentand align the significands; (3) Add or subtract significands; (4) Normalize the results.The pipeline can be considered to have two parallel threads, one handling exponentsand one handling significands, and could start out like this:In this figure, the boxes labeled R refer to a set of registers used to hold temporary results.Complete the block diagram that shows at a top level the structure of the pipeline.

How the processor uses the address bus, the data bus, and the control bus to communicate with the system memory?2. Which of the following are unidirectional and which are bidirectional?a. Address Busb. Control Bus3.

What are registers and what are the specific features of the accumulator, index registers, program counter, and program status word?4. What is the size of the accumulator of a 64bit processor?5. What is the difference between an instruction mnemonic and its opcode?6. How are instructions classified into groups?7. A combination of 8bits is called a byte. What is the name for 4bits and for 16bits?8.

What is the maximum memory 8088 can access?9. List down the 14 registers of the 8088 architecture and briefly describe their uses.10. What flags are defined in the 8088 FLAGS register? Describe the function of the zero flag, the carry flag, the sign flag, and the overflow flag.11.

Give the value of the zero flag, the carry flag, the sign flag, and the overflow flag after each of the following instructions if AX is initialized with 0x1254 and BX is initialized with 0x0FFF.a. Add ax, 0xEDABb. Add bx, 0xF00112. What is the difference between little endian and big endian formats? Which format is used by the Intel 8088 microprocessor?13.

For each of the following words identify the byte that is stored at lower memory address and the byte that is stored at higher memory address in a little endi an computer.a. What are the contents of memory locations 200, 201, 202, and 203 if the word 1234 is stored at offset 200 and the word 5678 is stored at offset 202?15. What is the offset at which the first exeutable instruction of a COM file must be placed?16. Why was segmentation originally introduced in 8088 architecture?17.

Why a segment start cannot start from the physical address 55555.18. Calculate the physical memory address generated by the following segment offset pairs.a. What are the first and the last physical memory addresses accessible using the following segment values?a.

Write instructions that perform the following operations.a. Copy BL into CLb. Copy DX into AXc. Store 0x12 into ALd.

Store 0x1234 into AXe. Store 0xFFFF into AX21. Write a program in assembly language that calculates the square of six by adding six to the accumulator six times.